1. Fields
The present invention relates to an information processing apparatus of a multiprocessor configuration having cache memories, and, more particular to a snoop control method and an information processing apparatus for reducing time for processing a memory access request.
2. Description of the Related Art
Conventionally, various technologies for quickly executing a memory access request in information processing apparatuses of a multiprocessor configuration having cache memories have been devised. For example, in the conventional technology described in Japanese Laid-open Patent Publication No. 1999-328026, a local processor automatically updates an invalid data item, which is stored in cache memories in relation to an effective address tag, with valid data without issuing an explicit reading or writing request by adding anew, as states of cache memories, a hovering state indicating that an address tag is valid but a data item stored in a corresponding way of a data array is invalid and a recent state indicating which cache memory among a plurality of cache memories that store copies of data items has recently received shared data via a transaction on a mutual connection line in addition to a change state, an exclusive state, a shared state, and an invalid state of a normal cache protocol (an MESI protocol, etc.).
Consequently, data invalidated by an activity of a remote processor is refreshed before the data is accessed by the local processor. Therefore, it is unnecessary to retrieve data from a remote cache memory or a system memory and it is possible to reduce waiting time for access to the cache memory or the system memory.
It is assumed that, in an information processing apparatus of a multiprocessor configuration having shared memories including a plurality of processors, which have cache memories, a plurality of input/output devices, and a plurality of memory devices (main memories), the processors, the input/output devices, and the main memories are divided into a plurality of groups and a system controller that manages the processors, the input/output devices, and the main memories is provided for each of the groups.
When the system controller receives a memory access request from a processor managed by the system controller, the system controller notifies other system controllers of the memory access request. The respective system controllers execute snoop processing for detecting states of data stored in cache memories in processors managed by the system controllers and states of resources (control buses, address buses, and data buses for chip select signals, read/write control signals, and the like sent to the cache memories) used for data transfer and selecting statuses of the cache memories with respect to data (object data) requested by the memory access request.
Each of the system controllers notifies the other system controllers of the status of each of the cache memories selected by the snoop processing as a snoop processing result, merges statuses of all the cache memories in the apparatus to determine a final status, and executes memory access start processing for starting memory access processing for inter-memory data transfer among the cache memories or between the cache memories and the main memories based on the determined final status.
In such a conventional information processing apparatus, three statuses, i.e., “BUSY” indicating that data transfer of object data is impossible, “HIT” indicating that data transfer of object data is possible, and “MISS” indicating that object data is not present in cache memories are defined. The system controller selects “BUSY” as a status when the system controller detects that data requested by a memory access request set as an object of the snoop processing (an object memory access request) (object data) and object data of a memory access request set as an object of memory access start processing and memory access processing, i.e., a memory access request issued before the object memory access request and set as an object of the memory access start processing and the memory access processing (a prior memory access request) conflict with each other or resources for data transfer are exhausted.
The system controller selects “HIT” when the system controller detects that the object data is present in the cache memories of the processor, the object data does not conflict with the object data of the object memory access request, and the resources for data transfer are not exhausted. The system controller selects “MISS” when the system controller detects that the object data is not present in the cache memories of the processor and the resources for data transfer are not exhausted.
The system controller sets the final status as “BUSY” when “BUSY” is present in statuses of all the cache memories, sets the final status as “HIT” when “BUSY” is not present and “HIT” is present, and sets the final status as “MISS” when all the statuses are “MISS”. In other words, the status “BUSY” has highest priority and the status “HIT” and the status “MISS” have lower priority in this order. The system controller sets a status having highest priority among all the statuses as the final status.
The system controller retries the snoop processing when the final status is “BUSY”. When the final status is “HIT” and the memory access request is a shared fetch request for referring to the object data, the system controller starts memory access processing for requesting one of the cache memories, for which “HIT” is selected as a status, to perform data transfer. When the final status is “HIT” and the memory access request is an exclusive fetch request based on a premise that the object data is updated, the system controller starts memory access processing for requesting one of the cache memories, for which “HIT” is selected as a status, to perform data transfer and invalidating the other cache memories, for which “HIT” is selected as s status. When the final status is “HIT” and the memory access request is a store request for storing data, the system controller starts memory access processing for invalidating all the cache memories, for which “HIT” is selected as a status, and storing the object data in the main memories. When the final status is “MISS” and the memory access request is the shared fetch request or the exclusive fetch request, the system controller starts memory access processing for reading data from the main memories. When the final status is “MISS” and the memory access request is the store request, the system controller starts the memory access processing for storing the object data in the main memories.
It is assumed that a status of a certain cache memory is “BUSY” and a status of at least one of the other cache memories is “HIT”. The system controller determines “BUSY” having the highest priority as the final status. As described above, “BUSY” is selected as a status when there is a conflict of the object data or the resources for data transfer are exhausted. When “BUSY” is selected because of the conflict of the object data, it is likely that data of the cache memories is changed by the memory access processing for the prior memory access request. Therefore, it is necessary to retry the snoop processing until the memory access processing for the prior memory access request is finished and states of the cache memories are fixed.
On the other hand, when there is no conflict of the object data and “BUSY” is selected as a status because the resources for data transfer are exhausted, access to the cache memories is impossible. However, because there is no conflict of the object data, even if the memory access processing for the prior memory access request is executed, data in areas of the cache memories that store the object data of the object memory access request is not updated. In other words, states of the cache memories in areas concerning the object data of the object memory access request are not changed. Therefore, it is possible to use data stored in the cache memories, for which “HIT” is selected as a status.
However, in the conventional information processing apparatus, there is a problem in that, when at least one cache memory, for which “BUSY” is selected as a status, is present in all the cache memories, the final status is “BUSY” and, even when usable data is actually present, retry of the snoop processing occurs, waiting time for access to the cache memories increases, and, as a result, processing time for a memory access request increases.